University of California, San Francisco (UCSF) postdoctoral scholar Nikhil Deveshwar, PhD, presented "Deep Generative Hardware Accelerated MRI" at the October UCSF Center for Intelligent Imaging (ci2) SRG Pillar Meeting. His talk addressed two bottlenecks in deep learning MRI reconstruction, the scarcity of raw multicoil training data and the compute these models require.
His research interests include MRI reconstruction, deep generative models for synthetic data, mixed-precision arithmetic for scientific computing, and hardware-software co-design for medical imaging. He received his PhD in Bioengineering from the UC Berkeley-UCSF Joint Program and an MS in EECS from UC Berkeley.
Deveshwar described unrolled optimization networks as the state of the art in deep learning MRI reconstruction, but they need large amounts of diverse raw multicoil training data. Existing datasets such as FastMRI, he noted, are limited in anatomy, pathology, scanner, protocol, and demographic diversity.
Hospital archives offer anatomy and pathology diversity at scale, but their images are magnitude-only. Deveshwar's approach feeds a magnitude image into a generative model to produce multiple plausible phase images, then combines them with coil sensitivity maps randomly sampled from a curated RF coil library to create synthetic multicoil training data.
On the FastMRI brain dataset, a model trained on 5% real data plus 20% synthetic data outperformed one trained on the full real dataset in PSNR, SSIM, and LPIPS. Deveshwar also noticed hallucinated fine structures that whole-image metrics missed, and said region-of-interest metrics will matter more for future testing and deployment.
The second half of his presentation turned to compute, which can limit deep learning reconstruction for large 3D volumes, high coil counts, real-time MRI, and portable MRI.
Deveshwar noted that "medical imaging has always been at the forefront of computer hardware."
His strategy uses mixed precision, running computationally expensive operations in low precision, and cheaper ones in high precision. He wrote a custom CUDA kernel that stores k-space in a compressed 8-bit format and performs the FFT in 16-bit arithmetic on chip. It ran around 1.6 to 1.75 times faster than NVIDIA's 16-bit FFT and about 3.5 times faster than its 32-bit FFT.
For settings where GPUs do not fit low power, low cost, or low latency needs, Deveshwar is looking to custom hardware. During graduate school, running the Automap neural network on a matrix accelerator with 8-bit quantization was around 30 times faster than the CPU. He envisions a custom system-on-chip and said he would like to start with portable MRI.
Visit the ci2 events page to learn more about upcoming SRG Pillar meetings.
